This invention relates to semiconductor memory devices, and more particularly to a row decoder circuit for use in programming memory devices.
In conventional single bit per cell memory devices, the memory cell assumes one of two information storage states, either an on-state or an off-state. This combination of either on or off defines one bit of information. In bi-level memories, since the cells can only have two different values of threshold voltage, Vt, during the reading operation, it is only necessary to sense whether or not the addressed transistor is conductive. This is generally done by comparing the current flowing through the memory transistor biased with predetermined drain-to-source and gate-to-source voltages with that of a reference transistor under the same bias conditions, either directly through current-mode sensing or after a current-to-voltage conversion through voltage-mode sensing.
In programming a typical flash memory cell, a high potential (such as, for example, approximately 3-12 volts) is applied to the control gate of the cell, the source terminal is grounded, and the drain terminal is connected to a voltage of about 5 volts. This operation can be performed in an array by selectively applying the pulse to the word line which connects the control gates, and biasing the bit line which connects the drains. This is commonly known in the art as the hot electron injection method of programming flash memory cells. Hot electron injection is used to move charge into the floating gate, thus changing the threshold voltage of the floating gate transistor. By placing the high voltage on the control gate, this generates electrons to flow in the channel and some hot electrons are injected on to the floating gate and change the potential of the floating gate to be more negative. Therefore, injection tends to saturate and the threshold voltage of a floating gate transistor follows the same trend. The state of the memory cell transistor is read or sensed by placing an operating voltage (for example, approximately 4-6 volts) on its control gate and approximately 0.5-1.0 volts on the drain, and then detecting the level of current flowing between the source and drain to determine which memory state the cell is in.
Programming and sensing schemes for multi-level memory devices are more complex, typically requiring 2nxe2x88x921 voltage references, where n is the number of bits stored in the cell. With reference to FIG. 5, an example of a prior art multi-level memory device is shown having two bits per cell which corresponds to four memory levels having three voltage references. A first memory level 321, represented by the binary number 11, is the state in which the memory cell has no charge. The memory level 324 in which the memory cell is fully charged is represented by the binary number 00. (The terms xe2x80x9cno chargexe2x80x9d and xe2x80x9cfully chargedxe2x80x9d are used herein, and throughout this discussion, for the purposes of explanation and are not intended to be limiting. For example, the (11) state could have a slight amount of charge and the (00) state could have less than the absolute maximum amount of charge.) In between the uncharged state (11) 121 and the fully charged state (00) 324 are a first intermediate level 322, represented by the binary number 10, in which the memory cell has a small amount of charge, and a second intermediate level 323, represented by the binary number 01, in which the memory cell has more charge than the 10 state but is not fully charged. The threshold voltages (Vt) shown in between each of the memory states of the memory cell represent the threshold voltages needed to transition between memory cell states. As discussed for a two-bit cell having four memory levels, there are three voltage references 311, 312, 313. For example, at the threshold voltage of 2.5 volts, the memory state is at the reference level 311 where the state of the cell will transition from the 11 state to the 10 state. At a voltage threshold Vt=3.5 volts, the memory cell is at the reference level 312 where the state of the cell will transition from the 10 state to the 01 state. And at the voltage threshold of Vt=4.5 volts, the memory cell is at the reference level 313 where the state of the cell will transition from the 01 state to the 00 state. The threshold voltage values shown in FIG. 5 are merely illustrative and the actual values of Vt will depend on the construction of the memory cell.
One of the main difficulties in implementing multi-level nonvolatile memory cells is being able to accurately program the cell, i.e. to place just the amount of charge on the floating gate of the cell transistor that is required to obtain the target value of the threshold voltage. The usual manner that is used in the prior art to deal with the problem of accurate charge placement is by using a cell-by-cell program and verify approach. In the program and verify approach, the programming operation is divided into a number of partial steps and the cell is sensed after every step to determine whether or not the target threshold voltage is achieved, so as to continue the programming if this is not the case. As each cell is independently controlled during programming, this technique allows simultaneous programming of a whole byte or even a number of bytes. This procedure ensures that the target Vt is reached, with the accuracy allowed by the quantization inherent in the use of finite programming steps. However, this process can be very long and must be controlled by on-chip logic circuitry.
A typical program and verify technique is illustrated in FIG. 6. As shown in FIG. 6, the programming of the memory cell is implemented by an alternating sequence of programming and verifying voltage pulses. The voltage 330 of each programming pulse incrementally increases with respect to time 332 until the desired target voltage is reached. The voltage level of the verify pulse remains constant throughout the programming process. For example as shown, after a first verify pulse 351, a first programming pulse 341 is implemented, and then a second verify pulse 352 follows. A next programming pulse 342 of an incrementally increased potential is applied, followed by a verify pulse 353, followed by a third programming pulse 343 which is increased in voltage from the previous programming pulse 352, followed by a third verify pulse 354 and so on, until the final programming pulse 347 is applied to allow the cell to reach the threshold voltage of the desired memory state. As can be seen in FIG. 6, the shape of the graph resembles a staircase, and this programming method is generally known in the art as staircase gate voltage ramp programming. This staircase method is described in numerous patents, including, for example, U.S. Pat. Nos. 5,043,940; 5,268,870; 5,293,560; and 5,434,825.
Each of the memory cells are arranged in rows (wordlines) and columns (bitlines) in a memory array. Typically, in a flash-type memory array, all of the gate terminals of the cells in a row are connected to the same wordline, while all of the drains of the cells in a column are connected to the same bitline; the sources of all the cells in the sector are connected to a common source line. This arrangement is typically repeated 8 or 16 times to obtain either byte or word output. Outputs of other bit lengths are also possible. In order to address the data in the memory cells within the memory array, row decoder (also referred to as an x-decoder) and column decoder (y-decoder) circuits are used to select the desired memory cells.
As explained above, the programming and verifying (reading) steps in programming both single bit per cell and multi-level memory cells are carried out by applying either a programming pulse or a verify (read) pulse on the control gate of the cell. Since the control gate of the cell is connected to the wordline of the memory array, the wordline is connected to the power supply line on which the programming or verify voltage is supplied. With reference to FIG. 4, a wordline 217 is connected to the control gates (not shown) of each of the memory cells in a particular row of the memory array. A select signal 212 is supplied to a wordline select circuit 213 in the the row decoder 214 to select a memory cell connected to that particular wordline 217. A voltage power supply line 225 is connected to the wordline select circuit 213 to supply the programming or verify pulses for programming the memory cell. As previously explained, the programming voltage is generally different (approximately 3-12 volts) than the verify (read) voltage (approximately 5-6 volts). Therefore, the voltage on the power supply line 225 must be changed back and forth between the programming voltage and the verify voltage. Switching the voltage on the power supply line limits the ability to have programming and verify pulses of a short duration, and thus limits the overall speed of the programming. Additionally, in the multilevel approach, switching the voltage on the power supply line limits the ability to accurately control the programming algorithm.
It is the object of the present invention to provide a row decoder circuit for a memory cell that eliminates the need to change the voltage on the power supply line during the programming of the memory cell.
The above object has been achieved by a row decoder circuit having means for selecting the wordline of a memory cell to be programmed and having a wordline driver circuit that receives voltages from a pair of separate power supply lines connected to the wordline, including a first power supply line that provides a programming voltage and a second power supply line that provides a read/verify voltage. The wordline driver circuit of the row decoder includes means for switching between the two power supply lines to provide one of the voltages to the wordline. Because the circuit switches between two power supply lines rather than requiring the voltage on a single power supply line to be changed, this allows for shorter programming and read/verify pulses to be used and allows for faster overall programming throughput. The row decoder circuit also provides better control in programming multi-level memory cells, and power savings due to the elimination of parasitic voltages commonly found in prior art row decoder circuits.